1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly, this invention relates to a process which inhibits cracking of a layer of low dielectric constant dielectric material on an integrated circuit structure.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, capacitance has increased between such conductive elements. This increase in capacitance results in loss of speed and increased cross-talk. As a result, reduction of such capacitance has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled xe2x80x9cPursuing the Perfect Low-K Dielectricxe2x80x9d, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH3xe2x80x94SiH3) with hydrogen peroxide (H02) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400xc2x0 C. to remove moisture.
The use of this type of low k material has been found to result in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the capacitance between such adjacent metal lines on the same metal wiring level.
The formation, from the reaction of silane (SiH4) with hydrogen peroxide (H2O2), of a flowable polymer-like dielectric material capable of providing void-free filling of high aspect ratio regions between parallel closely spaced apart metal lines with dielectric material has been known in the prior art for some time. Dobson U.S. Pat. No. 5,874,367, filed Jun. 30, 1993, and issued on Feb. 23, 1999, describes the formation of such a polymer-like dielectric material and its use as a planarization material. Dobson describes the formation of a first underlayer described as an adhesion enhancer, and then the formation of a layer of the flowable dielectric material, which is initially subject to a reduced pressure heat treatment to remove water prior to subjecting the polymer to a more intense heat treatment to solidify the polymer. However, before the intense heat treatment, Dobson forms a capping layer over the polymer layer. The capping layer is said to assist in providing mechanical stability for the polymer layer during the cross linking which occurs as the polymer loses further water during the further heating. Dobson further states that the capping layer may also help to control the rate as which the layer looses water during such further heating and so may have a controlling affect on shrinkage and cracking.
An article published by Dobson et al. in the December 1994 edition of Semiconductor International, at pages 85-88, entitled xe2x80x9cAdvanced SiO2 Planarization Using Silane and H2O2xe2x80x9d, further describes the formation of a planarizing layer of SiO2 by the reaction of silane (SiH4) with hydrogen peroxide (H2O2). The article further describes the formation of an underlayer of PECVD oxide and a capping layer of PECVD oxide. Both the underlayer and capping layer are said to be formed using a standard silane/nitrous oxide gas mixture. The capping layer of PECVD oxide is said to be 500 nanometers (nm) in thickness, and the authors report that the action of the capping layer reduces further the OH content of the flow layer and significantly improves the cracking resistance of the finished layer. Baking at 450xc2x0 C. for 30  minutes is said to almost completely remove hydrogen-bonded OH groups, producing a homogeneous amorphous silicon dioxide film.
Subsequent to this, McClatchie et al., in a paper entitled xe2x80x9cLow Dielectric Constant Oxide Films Deposited Using CVD Techniquesxe2x80x9d presented to the DUMIC Conference on Feb. 16-17, 1998, and published in the 1998 Proceedings Fourth International Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC) at pages 311-318, described formation of a low dielectric constant (low k) dielectric material which also exhibits flowable properties and is formed by reacting a methyl silane (CH3SiH3) with hydrogen peroxide (H2O2). McClatchie et al. also describe the use of an underlayer and a capping layer with the flowable low k dielectric layer, stating that the underlayer functions as a moisture barrier and as an adhesion layer, while the capping layer is said to provide mechanical stability during the final anneal step.
The use of a moisture barrier layer beneath a flowable low k dielectric layer, formed by reacting a carbon-substituted silane with hydrogen peroxide, protects underlying materials, such as the silicon substrate or underlying metal lines, from exposure to the moisture and other reaction products formed and released as the flowable low k dielectric layer cures during high temperature annealing. However, it has been found, during the formation of vias and other openings through such low k dielectric material, that a low k dielectric material, formed by the reaction of carbon-substituted silane and hydrogen peroxide, may be sensitive to moisture and other chemicals, necessitating the need for a capping layer over the upper surface of the low k silicon oxide dielectric material to protect the otherwise exposed upper surface of the low k layer from such materials.
The use of such a protective capping layer, formed using dielectric materials such as silicon oxide or aluminum oxide, having (in the case of silicon oxide) either a conventional dielectric constant of about 4 or higher, or a low dielectric constant of 3.5 or lower, is described in copending U.S. Patent application Ser. Nos. 09/428,344; 09/590,310; 09/574,771; and 09/607,512; and in U.S. Pat. Nos. 6,114,259 and 6,028,015; all assigned to the assignee of this invention. Furthermore, while not providing for capping layers per se thereon, copending U.S. patent application Ser. Nos. 09/425,552; 09/426,056; and 09/605,380; all assigned to the assignee of this invention, disclose the formation of a further oxide layer over a layer of low k silicon oxide dielectric material.
The problem of cracking of a layer of low k silicon oxide dielectric material is also known. Copending U.S. patent application Ser. No. 09/346,493, assigned to the assignee of this application, teaches the formation and individual annealing of a series of thin layers of low k silicon oxide dielectric material to change the residual stress in the composite layer to a compressive stress rather than tensile stress, since the normal tensile stress of the layer of low k silicon oxide dielectric material is considered to be likely to cause cracking of the layer of low k silicon oxide dielectric material.
Copending U.S. patent application Ser. No. 09/605,382, assigned to the assignee of this application, also recognizes the problem of cracking in layers of low k silicon oxide dielectric material and proposes to treat the material with hydrogen to reduce such cracking.
While it would be desirable to inhibit cracking of the layer of low k silicon oxide dielectric material by a capping layer of conventional silicon oxide having a compressive stress which would counter the tensile stress of the layer of low k silicon oxide dielectric material, the compressive stress of a xcx9c50 nm (500 Angstrom) conventional silicon oxide capping layer (used as a protective layer to inhibit penetration of moisture and other chemicals to the underlying low k silicon oxide dielectric material) is typically only about 1xc3x97109 dynes/cm2. To provide sufficient compressive stress needed to counter the tensile stress of the low k silicon oxide dielectric layer would require the use of a much thicker layer of conventional silicon oxide, possibly as high as 500 nm as reported by Dobson et al. for their capping layer over their layer of conventional (non-low k) flowable silicon oxide formed by reacting silane with hydrogen peroxide. However, the combination of high dielectric constant and thickness of such a capping layer of conventional silicon oxide would, in turn, negatively impact upon the overall dielectric constant of the composite layer of lower barrier layer, low k layer, and upper capping layer, since such a thick, high dielectric constant capping layer would comprise a considerable portion of the overall thickness of the composite layer.
It would, therefore, be desirable to provide a composite layer including a layer of low k silicon oxide dielectric material and a capping layer of silicon oxide wherein the tensile stress developed by the layer of low k silicon oxide dielectric material did not result in the cracking of the layer of low k silicon oxide dielectric material during subsequent annealing of the structure and the overall dielectric constant of the composite layer was not significantly raised by the presence of the capping layer.
The invention comprises a process which inhibits cracking of a layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of the layer of low k silicon oxide dielectric material. The process comprises: forming a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate; and forming over the layer of low k silicon oxide dielectric material a capping layer of dielectric material having: a dielectric constant not exceeding about 4; a thickness of at least about 300 nm; and a compressive stress of at least about 3xc3x97109 dynes/cm2.